Solid state Random Access Memories (RAM), presently based on silicon technology, are the most important high-speed, reprogrammable memories in computer systems today. The content of a memory bit is stored in a circuit element called a cell, fabricated in a silicon Integrated Circuit (IC) chip. Each cell can exist in one of two stable states to represent a “0” or a “1.” A word is stored in a particular group of cells in a memory array and can be identified with, and addressed by, a unique numerical address. Thousands to millions of cells can be fabricated in a single Very Large Scale Integrated (VLSI) chip along with additional address decoding and read/write control circuits. Given the address of any word, the memory content of that word can be retrieved during a memory operation time cycle, typically between 5 and 200 nsec. Any given bit can be addressed, written, rewritten, read and reread repeatedly, with fast access, read and write times. The desired attributes of RAM include high speed, low power dissipation, high packing density, and inexpensive manufacturing cost. Although the technology for address decoding, read/write control and read sensing is fairly standard, the kind of circuit element that is used to comprise each memory cell can vary widely and is the subject of much research and development.
Conventional DRAM
The Dynamic Random Access Memory (DRAM) cell is popular because the cell size can be made small, leading to a high packing density and relatively low cost. The storage element is a capacitor C and the two stable states can be, for example, the states with stored charge Q and with stored charge 0. Every cell is connected to an array of write and read wires, also called “bit” and “word” lines. Since one capacitor linked together with other capacitors in an array can lose its charge to its neighbor, the capacitor of each cell is connected to a transistor in that cell so as to isolate it from the array. When the transistor is “on” there is a low resistance to a write or read wire so that an applied voltage can charge the capacitor or a sense circuit can determine the stored charge. When the transistor is “off” there is a high impedance to the write or read wire which isolates the capacitor electrically from any other element in the array.
The packing density of DRAM memories has undergone steady improvement for more than two decades. Early DRAM cells used several capacitors and transistors, but now the most common designs use a single capacitor and single transistor because minimizing the number of elements in a cell allows the size of the cell to be reduced to a minimum. Typically, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is fabricated by standard lithographic processing techniques on a silicon substrate. The oxide that isolates the gate from the channel is highly insulating, so that the metallized gate has a capacitance to the rest of the device. In early designs, e.g. with 3 elements per cell, the gate capacitance was used as the storage capacitance. Single element cells use a MOSFET and a separate capacitor C. Reading is performed with a sense circuit that compares the charge (or voltage) of C with the charge (or voltage) of a standard capacitor C in a dummy cell. For an accurate readout, the charge Q stored on the capacitor must be the order of 1 million electrons or more. While FETs have benefited from advances in processing techniques so that they can be fabricated with dimensions smaller than a micron, capacitors have not benefited from similar gains in technology and it is still necessary for capacitors to have dimensions of order one micron or larger in order to hold the necessary charge. Thus, the size of DRAM memory cells is not decreasing as rapidly as processing technology would allow, and one significant drawback of DRAM is that reliable cells might never be fabricated on a submicron scale. Furthermore, the necessity of comparing capacitance with that of dummy cells requires the fabrication of dummy cells which take up extra space on the chip. A second disadvantage, for some cell designs, is that the read process drains whatever charge is stored on the capacitor. This phenomenon is known as “destructive readout” because the read process destroys the state of the cell (capacitor), and a rewrite circuit must be provided to rewrite the memory after every read. The rewrite circuit takes up space on the chip and the rewrite process can lengthen the amount of time of the read cycle. A third weakness is that the capacitor plate of any cell is never perfectly isolated. There is always some finite impedance to ground which permits the charge to leak from the capacitor, and in this process the memory is also lost. To remedy this, a refresh circuit is used to rewrite the memory constantly, typically once every few milliseconds. The refresh circuit takes up space on the chip, uses Central Processing Unit (CPU) time, lengthens the time of the read cycle, and dissipates extra power [typically 0.1 to 0.2 watts per megabyte of RAM]. The power dissipation is of particular concern for memories that are powered by batteries, such as laptop computers, mobile communications equipment, and satellite electronics. DRAM cells derive the name “dynamic” because the memory is dynamic, i.e. it is constantly being refreshed, and memory cells which lose their memory when not being powered are called volatile. A fourth problem with DRAM is that a particle radiation, either from background sources or from contaminants on the chip, can cause a spurious discharge of the capacitor and give a false reading. This is one of the largest error mechanisms limiting the reliability of DRAM.
More recently, cell circuit elements other than typical oxide dielectric capacitors have been proposed to serve as nonvolatile memory storage elements. The chief advantage of a Nonvolatile Random Access Memory (NRAM) is that memory is retained even when the array is not being powered. Thus, power dissipation is minimized since the array draws zero quiescent power. Furthermore, refresh circuitry is eliminated, thus saving space on the chip and requiring less time of the CPU. One category of nonvolatile circuit elements utilizes magnetic materials and their properties. For example, one kind of nonvolatile memory cell uses a circuit element similar to that of DRAM, but the dielectric material of the capacitor is ferroelectric, i.e. the capacitance has two different values for two different states of the dielectric which are determined by application of a magnetic field. Although this cell is nonvolatile, the dielectric properties of the ferroelectric material are relatively weak so that the size of the capacitor C must be fairly large and therefore the cell size is necessarily large. This structure has similar limitations to the oxide dielectric capacitors described above: the read process is destructive, the cells are susceptible to α particle radiation. Finally, the ferroelectric material degrades with time so that the cell is incapable of sustaining an infinite number of read and write cycles.
Other kinds of circuit elements for nonvolatile memory cells use ferromagnetic materials rather than ferroelectric materials. Two different approaches use magnetoresistive elements as the storage elements of the cell.
MRAM
Magnetoresistive Random Access Memory (MRAM) (described in an article by James Daughton, “Magnetoresistive Memory Technology,” Thin Solid Films 216, 162 (1992) which is incorporated by reference herein) employs an array of bit and word lines. Each bit line is divided into n storage cells. Each cell is a trilayer composed of a ferromagnetic metal base layer, a nonmagnetic metal middle layer, and a ferromagnetic metal top layer. The cell has length l, width w and thickness d. Looking at a cell in cross section across the width, there are two stable magnetizations states, each with the magnetization of the two ferromagnetic films oriented in opposing directions: clockwise and counterclockwise. The resistance of each cell, measured with a sense current applied along the length of the cell, is R1 when the magnetizations are perpendicular to the sense current (as is the case for the stable magnetization states) and R1′ if the magnetizations of the ferromagnetic layers are forced to lie parallel to the sense current. Each cell in the bit line is connected to the next cell with a conducting strip which has resistance Rc. Columns of n word lines cross the m rows of bit lines. Each nonmagnetic word line crosses the top of a cell in each bit line.
The state of cell (i,j) is written by sending current pulses of appropriate amplitude through bit line i and word line j, causing the magnetization of the cell to orient either clockwise or counterclockwise. The contents of the cell are read by first biasing word line j with a large enough current so that the magnetizations of both ferromagnetic layers are canted to an orientation that is approximately 45 degrees away from the axis of the bit line. In this orientation the resistance of the cell (for a sense current applied along the bit line) has a value R2 that is between R1 and R1′. Next, a sense current is applied along the bit line, and a voltage is measured across the bit line, having a value proportional to (n−1)R1+R2+nRc. Finally, a read current pulse is applied to the word line, in addition to the original bias current. This current pulse changes the magnetization orientation in a direction more nearly parallel to the sense current if the initial orientation was clockwise, or in a direction more nearly perpendicular to the sense current if the initial orientation was counterclockwise. Thus, the voltage across the bit line either increases or decreases when the read pulse is applied. A sense circuit that measures changes of voltage [a derivative circuit] records the positive or negative change as a “1” or a “0.”
By using a derivative sense technique, MRAM avoids the necessity of electrically isolating each cell. However, the signal to be sensed is quite small and the signal to noise ratio is poor. The change in resistance that must be sensed during the read process is a small fraction of R1, and this small change must be distinguished from a background of approximately n(R1+R2). In practice, two elements are fabricated for each cell [thus doubling the signal], and the read process is repeated several times so that the final readout is taken as an average of repeated samplings [thus lowering the noise]. This increases the time for a read cycle. Power dissipation is relatively large during readout because relatively large currents must be applied to long, resistive lines. Finally, errors can be introduced during readout if the bias current tips the magnetization into an unstable state.
NRAM with Magnetoresistive Element
Another approach uses a magnetoresistor R as the storage element, and the cell is comprised of R, a reference resistor R′, and means (such as one or more FETs) to isolate the cell from the rest of the array. The magnetoresistor R is typically a thin film ferromagnetic metal (or ferromagnetic/nonmagnetic metal multilayer) resistor with length l, width w and thickness d, and has two values, R′ and R′+δR, corresponding to two stable magnetization states. For example, in one state the magnetization of a permalloy film might be parallel to the direction of flow of the sense current, Isense, and in the other state the magnetization might be perpendicular to Isense. The magnetization state is written by using the magnetic field generated by current pulses applied to an array of write wires. The read process begins by selecting a cell, for example by switching the isolating FETs to the “on” state by driving the appropriate word line to a high voltage. A bias current Isense is applied to the magnetoresistor R and the reference resistor R′. A sense circuit at the end of a line of cells compares the two voltages and interprets a “1” or “0” when, for example, Isense*(R−R′)>0 or Isense*(R−R′)=0 respectively. The voltage levels corresponding to “1” (and “0”) are then amplified to TTL or CMOS levels. The voltage Isense*δR that distinguishes a “1” from a “0” must be large enough for reliable discrimination. Since the magnetoresistive ratio δR/R′ of ferromagnetic films (or multilayers) is small, 10 percent or less, the magnetoresistor must be made quite large. For example, with R′=100 Ω and δR/R′=0.1, a reasonable bias current of 1 mA would produce a detectable voltage difference of 10 mV.
This approach has several disadvantages. Resistors require substantial area in a cell. For example, the 100 Ω magnetoresistor could be fabricated, using ferromagnetic materials with resistivities of about 20 μΩ-cm, with a length l=5 μm, width w=1 μm, and thickness d=0.01 μm. Since this cell requires the fabrication of two resistors, substantial space is used. The reference resistor cannot be placed outside the cell because the resistive difference, δR, is so small that the resistance of each cell must be matched to a particular reference. Since resistance is a function of temperature, R=R(T), the reference resistor must be fabricated very near the magnetoresistor so that both resistors will always be at the same temperature, and the material for the reference resistor must be carefully chosen so that the temperature dependence of its resistivity is similar to that of the magnetoresistor. Finally, the resistance of each cell is quite large. When numerous cells are placed on a single read line, as in an array, the resistance of the read line is substantial. Since the read process uses current bias, the power dissipated in each read cycle is relatively large.
Magnetic Spin Transistor
The Magnetic Spin Transistor is described in recent articles (see, e.g., Mark Johnson, “The All-Metal Spin Transistor,” IEEE Spectrum 31 (5), 47 (1994), and Mark Johnson, “The Bipolar Spin Switch,” Science 260, 320 (1993), which are incorporated by reference herein) as a novel device that can be used as a circuit element in a nonvolatile memory cell. Two characteristics of the device must be considered when using the device in an NRAM array. First, the device can be fabricated entirely from metals, and is therefore characterized by a low electrical impedance. Thus, to fabricate an array of such elements it is necessary to electrically isolate each element from others in the array, so that the output of any element will not be shorted to ground through a neighboring element. Second, [like many other memory elements] the output voltages available from the device are less than TTL or CMOS levels, and the output must therefore be amplified before it is incorporated in TTL or CMOS circuits.
Previous NRAM cell designs using the spin transistor as a memory element have approached the above constraints in two ways. In the first, the memory cell is comprised of a spin transistor and a differential amplifier. The amplifier also provides cell isolation. The drawback of this approach is that each cell requires a significant amount of space on a chip, and the complicated fabrication procedures required for circuits composed of numerous transistors will drive up the cost per bit of the memory. In the second approach, the cell is composed of a spin transistor and one or more capacitors and resistors. The passive elements provide isolation for the spin transistor of each cell, and the readout voltage is transmitted to the end of a line of elements where amplification is performed. The disadvantage here is that passive circuit elements, in particular resistors and capacitors, require substantial space on a chip. Thus, the majority of cell area is occupied by passive elements and packing densities are limited. Furthermore, cell isolation is not very efficient and the readout voltage can be degraded during transmission to the sense circuit, resulting in higher noise and lower readout sensitivity.